1. Technical Field of the Invention
The embodiments of the invention relate to scan testing of integrated circuits and, more particularly, to a PLL-based at-speed scan testing scheme.
2. Description of Related Art
Generally, integrated circuits are tested after manufacture to ensure that the integrated circuits are not operationally defective. One testing technique employs the use of scanning vectors, in which a particular test vector is shifted into an integrated circuit (IC) prior to running the IC's combinational logic in its normal mode. A resultant output vector is then read to determine the response of the IC to the scanned in test vector. For high complexity ICs, one popular technique is the use of scannable flip-flops in the IC for scan testing. Some ICs employ full scan techniques, in which all of the flip-flops in the IC design are made scannable. Scannable flip-flops allow a test vector to be shifted in to load the flip-flops with a known pattern. Then, the IC is operated to allow the IC's normal circuitry to respond to the test vector, which response is captured by the flip-flops. Subsequently, the state of the scannable flip-flops are read out to determine the response of the IC to the initial test vector.
In a typical scan operation, a test vector is shifted into the IC by use of a scan clock to set the state of the flip-flops. The same scan clock is also used to scan out the state of the flip-flops after capturing the circuit response to the test vector. Since the scan shifting is performed while the IC is not operating normally, the scan clock may have a much slower clock frequency than the operational clock frequency of the IC. In some modes of testing, the slower scan clock may be adequate to capture the response of the internal circuitry. This technique is sometimes referred to as regular scan or DC scan. However, with much of the highly integrated and faster devices of today, it is typically the practice to employ faster clocks to perform the capture. The use of a faster clock for capture allows testing of the internal circuitry to be performed at normal operating speeds of the IC to more accurately portray the normal operational response of the circuitry. The technique of using a faster clock to capture the response of the IC to scan testing is generally referred to as at-speed scan or AC scan.
Although at-speed scan techniques exist, these known techniques utilize an external signal to indicate when the at-speed testing is to commence. That is, a separate external signal is utilized to initiate the capture of the internal states.
Furthermore, many ICs now employ more than one clock domain on a chip. If two or more clock domains in the IC communicate with one another, then the simultaneous testing of the different domains using scan test vectors may be difficult to achieve, since each vector tests one domain at a time. Specialized register programming may be necessary to specify which clock domains are to capture the at-speed data to an input test vector. However, these techniques present challenges to ICs employing multiple clock domains, where there is communication between the clock domains.